Complementary metal oxide semiconductor (CMOS) devices (e.g., NMOS or PMOS transistors) have conventionally been fabricated on semiconductor workpieces with a single crystal orientation (e.g., silicon having a Miller index (100)). Transistors within the CMOS devices, for example, are used in cell phones, laptop computers, etc., requiring greater speed, lower power consumption, higher reliability, and the like. The speed of the devices can be improved by increasing electron mobility, hole mobility, or both, using hybrid orientation technology (HOT). Electron mobility/movement for NMOS devices, for example, is high (e.g., 2-4 times higher) when the NMOS devices are built on a Miller index (100) substrate, however the hole mobility for PMOS devices is enhanced when the PMOS devices are fabricated on a Miller index (110) substrate. As a result, PMOS devices formed on a Miller index (110) surface will exhibit significantly higher drive currents than PMOS devices formed on a Miller index (100) surface. In other words, there is a desire to exploit the substrate orientation with Miller index (110) for pFETs and Miller index (100) for nFETs, for example. Previous endeavors to take advantage of this difference between NMOS and PMOS devices has resulted in hybrid substrates with different surface orientations using workpiece composites to optimize the crystalline orientation of the NMOS and PMOS devices, for example.
Direct silicon bonded (DSB) substrates are fabricated by chemo-mechanically bonding a film of single-crystal silicon of a first crystal orientation onto a base substrate having a different or second crystal orientation. Unlike, silicon-on-insulator (SOI) substrates, DSB substrates demonstrate “bulk-like” properties.
The industry continues to seek new approaches to “force” electric charges to move at faster rates through the semiconductor device channels in an endless pursuit of increased circuit speeds and power consumption reductions. The ever decreasing size and scale of semiconductor device technology has presented numerous challenges. For example, gate leakage current due to sharp corner effects in thin silicon gate oxide is a more pronounced problem with smaller devices. These sharp features can also increase stresses, produce large electric fields, create dislocations in the silicon, and ultimately fail the device, for example.
Crystallographic planes are significant in both the semiconductor characteristics and applications since different crystallographic planes can exhibit significantly diverse physical properties. For example, surface density of atoms (i.e., atoms/cm2) on various crystallographic planes can differ substantially from each other. One of the standard notations for the various planes is the Miller indices that are used to denote the crystallographic planes and the directions normal to those planes. The general crystal lattice is represented by a set of unit vectors (e.g., a, b, and c) such that an entire crystal can be replicated by copying the unit cell of the crystal and duplicating it at a given integer offset along the unit vectors. For example, reproducing the basic cell at positions (na)a+(nb)b+(nc)c, wherein na, nb, and nc are integers. It is not a requirement that the unit vectors be orthogonal.
FIGS. 1-3 show cubic crystals, with basic vectors in the x, y, and z directions. Superimposed on the three crystal lattices are three different planes indicated by the gray surface “partial planes”. The planes are shown in relation to the crystal axes x, y, and z by a set of three integers (e.g., (i1i2i3)) where i1 corresponds to the crystal plane's intercept with the x-axis, i2 corresponds to the plane's intercept with the y-axis and i3 corresponds to the plane's intercept with the z-axis. Given that parallel planes are equivalent planes, the intercept integers are reduced to the set of the three smallest integers having the same ratios as the above intercepts. The Miller index (100), (010) and (001) planes correspond to the faces of a cube. The (111) plane intercepts the x, y, and z axis at 1, 1, and 1 respectively, and the plane is tilted with respect to the cube faces. In representing a negative axis intercept, the corresponding Miller index is given as an integer and a bar over the integer, similar to the (100) plane but intersecting the x axis at −1 instead of 1, for example.
Amorphization templated recrystallization (ATR) is an approach for providing planar hybrid orientation substrates. Silicon is easily amorphized by ion implantation and easily recrystallized by a subsequent annealing. FIGS. 4-10 outline examples of ATR methods for producing hybrid orientation silicon substrates. FIGS. 4-6 describe an ATR method for forming a bulk semiconductor hybrid orientation technology (HOT) substrate. FIG. 4 shows a starting substrate 400 comprising a lower single crystal semiconductor substrate 402 having a first crystal orientation (100) (Miller Index plane) in direct contact with an upper second single crystal semiconductor layer 404 having a second crystal orientation (110) different from the first orientation. The interface 406, which is located between the semiconductor layers 402 and 404, is typically formed by a workpiece bonding process (e.g., direct silicon bonded (DSB) substrate) that is normally hydrophilic. The structure in FIG. 4 is often referred to as a mixed orientation DSB wafer or DSB workpiece. The fabrication of the mixed orientation DSB workpiece is well known by those of ordinary skill in the art.
FIG. 5 illustrates a structure 500 which results after the mixed orientation direct silicon bonded structure of FIG. 4 is subjected to ion implantation 502 in selected areas to create localized amorphization regions 504 extending from the top surface of semiconductor layer 404 to a depth ending in the substrate layer 402 below the interface 406. During anneal, the amorphized silicon will recrystallize to match the orientation of the crystalline silicon with which it is in contact. It should be noted that this process can be implemented, for example, with the Miller Index (MI) (100) layer on top and the MI (110) layer on the bottom as opposed to the illustrated approach.
Subsequently, FIG. 6 shows a structure 600 which results from the structure of FIG. 5 after localized amorphization regions 504 (FIG. 5) have been recrystallized, with the semiconductor layer 402 as a template, to form a single crystal semiconductor region 602 with the orientation of first semiconductor 402 (FIG. 5). The resulting substrate now comprises two clearly defined single-crystal semiconductor regions with different surface orientations, e.g., non-amorphization regions 404 of the second semiconductor layer and amorphization/recrystallized regions 602. However, it should be noted that end-of-range defects 408 remain in the structure at an approximate depth based upon the implantation energy. These defects 408 are well known by those of ordinary skill in the art.
FIGS. 7-10 illustrate yet another example of a conventional ATR method for producing a semimconductor-on-insulator (SOI) hybrid orientation substrate. FIG. 7 shows a starting substrate structure 700 comprising a handle substrate 702, an insulator layer 704, and a first single crystal semiconductor layer 706 having a first crystal orientation in direct contact with a second single crystal semiconductor layer 708 having a second crystal orientation different from the first. The interface 710 between semiconductor layers 706 and 708 is typically formed by a workpiece bonding process.
FIG. 8 shows a structure 800 which results when the structure of FIG. 7 is subjected to ion bombardment 802 in selected areas to create localized amorphization regions 804 extending from the top surface of insulator layer 704 up to and ending in semiconductor layer 708 above interface 710. FIG. 9 shows a structure 900 which results from the structure of FIG. 8 after localized amorphization regions 804 have been recrystallized, using semiconductor layer 708 as a template to form single crystal semiconductor region 902 (FIG. 9) with the orientation of upper semiconductor 708. Upper semiconductor layer 708 is then removed by a process (for example, polishing, oxidation/wet etching, or the like) to produce substrate 1000 of FIG. 10. Substrate 1000 comprises two clearly defined single-crystal semiconductor regions with different surface orientations, e.g., non-amorphization regions 706 of the second semiconductor layer and amorphization recrystallization region 1004, on the insulator layer 704. Regions 706 and 1004 may be further thinned (again by processes such as polishing and/or oxidation/wet etching), if thinner semiconductor-on-insulator structures are desired.
FIGS. 11-13 represent a conventional approach to forming a CMOS hybrid orientation device utilizing amorphization templated recrystallization (ATR) prior to shallow trench isolation (STI) formation. FIG. 11 shows a starting mixed orientation direct silicon bonded substrate 1100 comprising a lower single crystal semiconductor substrate 1102 having a first crystal orientation (100) in direct contact with an upper second single crystal semiconductor layer 1104 having a second crystal orientation (110) (e.g., Miller Index) different from the first orientation. The interface 1106, which is located between the semiconductor layers 1102 and 1104, is typically formed by a workpiece bonding process. The workpiece bonding process is well known by one of ordinary skill in the art.
FIG. 12 illustrates a photoresist layer 1202 patterned on the PMOS region of device 1200, as shown in FIG. 11. The device 1200 is then subjected to ion implantation 1204 in the selected areas to create localized amorphization regions 1206 extending from below the lower surface of semiconductor layer 1104 within the first silicon layer 1102 to the top of the substrate layer 1104. The ion implantation 1204 can, for example, comprise silicon, germanium, and the like.
Subsequently, FIG. 13 shows the structure of FIG. 12 after localized amorphization regions 1206 have been recrystallized, with the semiconductor layer 1102 acting as a template, to form a single crystal semiconductor region 1302 with the orientation of first semiconductor 1102. The resulting substrate 1300 now comprises two clearly defined single-crystal semiconductor regions with different surface orientations, e.g., non-amorphization region 1104 of the second semiconductor layer and amorphization/recrystallized region 1302. In other words, the PMOS region maintains the original orientation (110) DSB layer 1104 and (100) bulk workpiece control. The ATR layer 1206 (FIG. 12) of the NMOS has been changed, for example, from first crystalline orientation (110) to second crystalline orientation (100). An STI 1306 can then formed, as shown. The formation of the STI 1306 is well known by those of ordinary skill in the art. The amorphized layer 1206 (FIG. 12) can be redone utilizing a solid phase epitaxy (SPE) process 1304 to align the buffer layer 1302 to the (100) surface 1102, so that the buffer layer 1302 becomes a (100) surface, as illustrated.
FIG. 14A is provided to show a transmission electron microscopy (TEM) image of border region defects, with the cut perpendicular to the workpiece notch prior to the formation of the STI. FIG. 14A illustrates a defect 1402 that occurs in the prior art method illustrated in FIGS. 11-13, for example during the “recrystallization process.” As the amorphized layer 1206 is redone utilizing the SPE process 1304, the layer 1408 wants to grow vertically as it is transformed from an amorphized (110) crystal to a (100) crystal during SPE. The (110) layer 1406 that has not been amorphized wants to grow laterally during SPE, thereby forming a defect 1402 shown in device 1400. As shown in FIGS. 14A and 14B, the workpiece 1410 is cut or cross-sectioned perpendicular to the workpiece notch 1412. As discussed, there is competition between the horizontal/lateral templating (110) and the vertical templating (100) as shown, wherein the crystallographic planes ((100) and (110)) cause the residual corner defects 1402, as illustrated in FIG. 14A. Subsequent STI trenches and STI can be formed that replace the angular morphology 1404 containing the defects 1402. However, the angular morphology 1404 has a given width and the STI width can be very small, and it may not be possible to replace all of the defects in the angular morphology 1404 with a given STI. FIG. 14B illustrates the workpiece 1410, workpiece notch 1412 and notch orientation 1414, wherein the workpiece 1410 is cut in cross-section with orientation 1416, as shown, perpendicular to the notch orientation 1414.
As illustrated for the device 1500 in FIGS. 15A and 15B, the workpiece 1510 is cut or cross-sectioned parallel to the workpiece notch 1512. There is competition between the horizontal/lateral templating (110) in area 1506 and the vertical templating (100) of area 1508 as shown, wherein the crystallographic planes ((100) 1508 and (110) 1506) cause the residual corner defects 1502, as illustrated in FIG. 15A. As mentioned above, subsequent STI can be formed to replace the angular morphology 1504 containing the defects 1502 shown in FIG. 15A. As discussed, the angular morphology has a given width for a given process and the STI width is or can be very small and it may not be possible to replace all of the defects 1502 in the angular morphology 1504 with a given STI width. FIG. 15B illustrates the workpiece 1510, workpiece notch 1512 and notch orientation 1514 wherein the workpiece 1510 is cut in cross-section orientation 1516, as shown, parallel to the notch orientation 1514. These illustrations clearly show the issues/problems/defects that are present with the conventional approach to performing ATR prior to STI formation. These defects can and have been corrected with extremely high temperature anneals (e.g., greater than 1250 degrees Celsius); however those temperatures can cause other defects, such as large stresses that can warp the workpiece, and the like.
FIGS. 16-18 represent a second conventional approach to forming a CMOS hybrid orientation device utilizing amorphization templated recrystallization (ATR) after STI formation. FIG. 16 shows a starting device 1600 comprising a lower single crystal semiconductor substrate 1602 having a first crystal orientation (100) in direct contact with an upper second single crystal semiconductor layer 1604 having a second crystal orientation (110) (e.g., Miller Index) different from the first orientation. As discussed above, the interface 1606, which is located between the semiconductor layers 1602 and 1604, is typically formed by a workpiece bonding process, e.g., DSB. Workpiece bonding processes are well known by those of ordinary skill in the art and all are contemplated herein.
FIG. 17 illustrates a device 1700 with an STI 1702 formed into and through the (110) Miller index layer 1604 and into a portion of the (100) handle substrate 1602, for example. The formation of the STI 1702 is well known by those of ordinary skill in the art. A photoresist layer 1704 is subsequently patterned on the PMOS region of the device 1700, as shown in FIG. 17. The device 1700 is then subjected to ion implantation 1706 in the selected areas to create localized amorphization regions 1708 extending from below the lower surface of semiconductor layer 1604 within the first silicon layer (100) 1602 to the top of the substrate layer 1604. The ion implantation 1706 can, for example, comprise silicon, germanium, and the like.
FIG. 18 shows the device of FIG. 17 after localized amorphization regions 1708 (FIG. 17) have been recrystallized, with the semiconductor layer 1602 acting as a template, to form a single crystal semiconductor regions (100) 1602 and 1806, both with the orientation of first semiconductor (100). The resulting device 1800 now comprises two clearly defined single-crystal semiconductor regions with different surface orientations, e.g., non-amorphization regions (110) 1604 of the second semiconductor layer and amorphization/recrystallized regions 1806. The amorphized layer 1708 (FIG. 17) can be redone utilizing a solid phase epitaxy (SPE) process 1804 to align the buffer layer 1708 (FIG. 17) to the (100) surface/layer 1602, so that the buffer layer 1708 becomes a (100) surface/layer, as illustrated. Advantages of this approach include no lateral templating; however there are trench edge and corner defects created using this technology from vertical templating and the like. The defects are created when the uniform recrystallization stops on the (111) plane (FIG. 3) because the (111) plane meets the surface of the STI at, for example, 54 degrees.
FIG. 19 shows an example transmission electron microscopy (TEM) image of border region defects of a device 1900, with the TEM cut parallel to the workpiece notch. FIG. 19 illustrates common defects 1902 that occur in angular morphology 1904 with the conventional method illustrated in FIGS. 16-18. As the amorphized layer 1708 (FIG. 17) is redone utilizing the SPE process 1804 (FIG. 18), the surface of the STI 1702 restrains the crystals from regrowing in an unrestrained manner.
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above.